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this is information on a product in full production. april 2013 docid024474 rev 1 1/35 35 L4984D ccm pfc controller datasheet - production data features ? line-modulated fixed-off-time (lm-fot) control of ccm-operated pfc pre-regulators ? proprietary lm-fot modulator for nearly fixed- frequency operation ? proprietary multiplier design for minimum thd of ac input current ? fast ?bi-directional? in put voltage feedforward (1/v 2 correction) ? accurate adjustable output overvoltage protection ? protection against feedback loop failure (latched shutdown) ? inductor saturation protection ? ac brownout detection ? digital leading-edge blanking on current sense ? soft-start ? 1% (at tj = 25 c) internal reference voltage ? - 600 / + 800 ma totem pole gate driver with active pull-down during uvlo and voltage clamp ? ssop10 package applications ? pfc pre-regulators for: ? iec61000-3-2 and jeida-miti compliant smps in excess of 1 kw ? desktop pc, server, web server ssop10 table 1. device summary order code package packaging L4984D ssop10 tube L4984Dtr tape and reel www.st.com
contents L4984D 2/35 docid024474 rev 1 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 typical electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 overvoltage protection (o vp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7 feedback failure detection (ffd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 voltage feedforward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9 soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10 inductor saturation detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 11 thd optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 12 power management and housekeeping functi ons . . . . . . . . . . . . . . . . 30 13 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
docid024474 rev 1 3/35 L4984D list of figures list of figures figure 1. electrical diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. ic consumption vs. v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 4. ic consumption vs. tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5. v cc zener voltage vs. tj. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 6. startup & uvlo vs. tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 7. feedback reference vs. tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 8. e/a output clamp levels vs. tj. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 9. uvlo saturation vs. tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 10. ovp levels vs. tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 11. inductor saturation threshold vs . tj. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 12. v cs clamp vs. tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 13. timer pin charging current vs. tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 14. brownout threshold (on vff) vs. tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 15. r ff discharge vs. tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 figure 16. line drop detection threshold vs . tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 17. v multpk - v vff dropout vs. tj. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 18. pfc_ok enable threshold vs. tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 19. ffd threshold vs. tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 20. multiplier characteristics at v ff =1 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 21. multiplier characteristics at v ff =3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 22. multiplier gain vs. tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 23. gate drive clamp vs. tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 24. gate drive output saturation vs. tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 25. delay to output vs. tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 26. line-modulated fixed-off-time modulator: a) internal block diagram; b) key waveforms. . . 17 figure 27. typical frequency change along a line half-cycle in a boost pfc operated in lm-fot (left) and tm (right) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 28. line-modulated fixed-off-time-controlled boos t pfc: current waveforms . . . . . . . . . . . . . . 19 figure 29. line-modulated fixed-off-time-controlled boost pfc: input current harmonic contents . . . 20 figure 30. output voltage setting, ovp and ffd functions : internal block diagram . . . . . . . . . . . . . . 21 figure 31. voltage feedforward: squa rer-divider (1/v2) block diagram an d transfer characteristic . . . 23 figure 32. r ff c ff as a function of 3rd harmonic distortion in troduced in the input current . . . . . . . . 25 figure 33. startup mechanisms and activa tions of the soft-start function . . . . . . . . . . . . . . . . . . . . . . 26 figure 34. effect of boost inductor saturation on mosfet current and detection method . . . . . . . . . 27 figure 35. thd optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 36. hd optimization: standard pfc co ntroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 37. interface circuits that let dc-dc converter contro ller ic disable the L4984D . . . . . . . . . . . 30 figure 38. sso10 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
description L4984D 4/35 docid024474 rev 1 1 description the L4984D is a current-mode pfc controller operating with line-modulated fixed-off-time (lm-fot) control. a proprietary lm-fot mo dulator allows fixed-frequency operation for boost pfc converters as long as they are operated in ccm (continuous conduction mode). the chip comes in a 10-pin so package and offers a low-cost solution for ccm-operated boost pfc pre-regulators in en61000-3-2 and jeida-miti compliant applications, in a power range that spans from few hundred w to 1 kw and above. the highly linear multiplier includes a special ci rcuit, able to reduce the crossover distortion of the ac input current, that allows wide-ra nge-mains operation with a reasonably low thd, even over a large load range. the output voltage is controlled by means of a voltage-mode error amplifier and an accurate (1% at tj = 25 c) internal voltage referenc e. loop stability is optimized by the voltage feedforward function (1/v 2 correction), which in this ic uses a proprietary technique that also significantly improves line transient response in the case of mains drops and surges (?bi-directional?). the device features low consumpt ion and includes a disable function suitable for ic remote on/off. these features allow use in applicatio ns which also comply with the latest energy saving requirements (b lue angel, energy star ? , energy 2000, etc.). in addition to overvoltage protection able to keep the output voltage under control during transient conditions, the ic is also provided wit h protection against feedback loop failures or erroneous settings. other onboard protection fu nctions allow that brownout conditions and boost inductor saturation can be safely handl ed. soft-start limits peak current and extends off-time to prevent flux runaway in the initial cycles. the totem pole output stage, capable of 600 ma source and 800 ma sink current, is suitable for big mosfets or igbt drive.
docid024474 rev 1 5/35 L4984D block diagram 2 block diagram figure 1. electrical diagram cs 1.66 v vff s r q1 leb q1 voltage regulator uvlo -+ - + 2.5 v - + multiplier ? internal supply bus voltage references vcc gd gnd mult inv timer uvlo disable q s r disable l_ovp uvlo error amplifier comp ideal rectifier 1/v 2 ovp + - 0.23 v - + disable ovp 2.5 v 2.4 v + - l_ovp 6 7 brownout 8 3 9 10 1 2 detector mains drop 4 5 + - 1.7 v stop driver & clamp - + 0.8 v 0.88 v brownout 0.27 v lm-fot modulator 300 us monostable 0.88 v stop pfc_ok am13217v1
block diagram L4984D 6/35 docid024474 rev 1 figure 2. pin connection (top view) table 2. absolute maximum ratings symbol pin parameter value unit v cc 10 ic supply voltage (icc = 20 ma) self-limited v - 1, 3, 6 max. pin voltage (i pin = 1 ma) self-limited v - 2, 4, 5, 7 analog inputs & outputs -0.3 to 8 v vff pin 5 maximum withstanding voltage range test condition: an si/esda/jedec js001 +/- 1500 v other pins 1 to 4 6 to 10 +/- 2000 v table 3. thermal data symbol parameter value unit rth j-amb max. thermal resistance, junction-to-ambient 120 c/w ptot power dissipation at t amb = 50 c 0.75 w tj junction temperature oper ating range -40 to 150 c tstg storage temperature -55 to 150 c table 4. pin functions n. name function 1inv inverting input of the error amplifier. the information on the output voltage of the pfc pre-regulator is fed into the pin through a resistor divider. the pin normally features high impedance. 2comp output of the error amplifier. a comp ensation network is placed between this pin and inv (pin 1) to achieve stability of the voltage control loop and ensure high power factor and low thd. to avoid uncontrolled rise of the output voltage at zero load, when the voltage on the pin falls below 2.4 v the gate driver output is inhibited (burst-mode operation). inv comp mult cs vff vcc gd gnd timer pfc_ok 1 2 3 4 5 6 7 8 9 10 am13218v1
docid024474 rev 1 7/35 L4984D block diagram 3mult main input to the multiplier. this pi n is connected to the rectified mains voltage via a resistor divider and provides the sinusoidal reference to the current loop. the voltage on this pin is used also to derive the information on the rms mains voltage. at startup this pin is used also to perform soft-start. this pin can also be used as a remote on-off control input by means of the internal brownout comparator. in this case the ic performs the soft-start function when the pin is released. 4cs input to the pwm comparator. the current flowing in the mosfet is sensed through a resistor; the resulting voltage is applied to this pin and compared to an internal sinusoidal-shaped referenc e, generated by the multiplier, to determine the turn-off instant of th e external power mosfet. the pin is equipped with about 220 ns digital leading-edge blanking for improved noise immunity. a second comparison level set at 1.7 v detects abnormal currents (e.g. due to boost inductor saturation) and, on this occurrence, activates a safety procedure that temp orarily stops the converte r and limits the stress of the power components. 5vff second input to th e multiplier for 1/v 2 function. a capacitor and a parallel resistor must be connected from the pin to gnd. they comp lete the internal peak-holding circuit that derives the information on the rms mains voltage. the resistor should range from 100 k (minimum) to 2 m (maximum). the voltage on this pin, a dc level equal to the peak voltage on pin mult (3), compensates the control loop gain dependence on the mains voltage. this pin is also internally connected to a co mparator in order to provide brownout (ac mains undervoltage) protection. a voltage below 0.8 v shuts down (not latched) the ic and brings its consumpt ion to a considerably lower level. the ic restarts as the voltage at the pin goes above 0.88 v. never connect the pin directly to gnd. 6pfc_ok pfc pre-regulator output voltage monitoring/disable function. this pin senses the output voltage of the pfc pre-regulator through a resistor divider and is used for protection purposes. if the voltage on the pin exceeds 2.5 v, the ic stops switching and restarts as the voltage falls below 2.4 v. however, if at the same time the voltage on the inv pin falls below 1.66 v, a feedback failure is assumed. in this case the device is latched off. normal operation can be resumed only by cycling v cc . if the voltage on this pin is brought below 0.23 v, the ic is shut down. to restart the ic the voltage on the pin must go above 0.27 v. this pin can also be used as a burst-mode control input to synchronize the burst-mode of the ic to the one of a d2d converter controller. do not use this pin as remote on/off control input because the soft-start function is performed only at the startup by pfc_ok but not on the following releases. 7 timer lm-fot modulator setting. a capacitor connected between this pin and ground is charged by an accurate internal generator during th e off-time of the external power mosfet (i.e. while pi n gd is low), ther efore generating a voltage ramp. as the voltage ramp equals the voltage on the mult pin, the off-time of the power mosfet is terminated, the gd pin is driven high and the ramp is reset at zero. 8gnd ground. current return for both the signal part of the ic and the gate driver. keep the pcb trace that goes from this pin to the ?cold? end of the sense resistor separate from the trace that collects the grounding of the bias components (output voltage sensing divider, multiplier bias divider and lm- fot modulator setting). table 4. pin functions (continued) n. name function
block diagram L4984D 8/35 docid024474 rev 1 9gd gate driver output. the totem pole output stage is able to drive power mosfets and igbts. it is capable of 600 ma source current and 800 ma sink current (minimum values). the high-level voltage of this pin is clamped at about 12 v to avoid excessive gate voltages in case the pin is supplied with a high v cc . 10 v cc supply voltage of both the signal part of the ic and the gate driver. sometimes a small bypass capacitor (0.1 f typ.) to gnd may be useful in order to get a clean bias voltage for the signal part of the ic. the voltage on the pin is internally clamped at 22.5 v min. to protect the internal circuits from excessive supply voltages. table 4. pin functions (continued) n. name function
docid024474 rev 1 9/35 L4984D electrical characteristics 3 electrical characteristics (tj = -25 to 125 c, v cc = 12 v, (a) ctimer = 470 pf, co = 1 nf between pin gd and gnd, c ff = 1 f and r ff = 1 m between pin vff and gnd; un less otherwise specified.) a. adjust v cc above v ccon before setting at 12 v. table 5. electrical characteristics symbol parameter test condition min typ max unit supply voltage v cc operating range after turn-on 10.3 22.5 v v ccon turn-on threshold (1) 11 12 13 v v ccoff turn-off threshold (1) 8.7 9.5 10.3 v v ccrestart v cc for resuming from latch ovp latched 5 6 7 v hys hysteresis 2.3 2.7 v v z zener voltage icc = 20 ma 22.5 25 28 v supply current i start-up startup current before turn-on, v cc = 10 v 65 150 a i q quiescent current after turn-on, v mult = 1 v 4 5 ma i cc operating supply current at 70 khz 5 6.0 ma i qdis idle state quiescent current v pfc_ok > v pfc_ok_s and v inv < v invd 200 280 a v pfc_ok < v pfc_ok_d 1.5 2.2 ma i q quiescent current v pfc_ok > v pfc_ok_s or v comp < 2.3 v 2.2 3 ma multiplier input i mult input bias current v mult = 0 to 3 v -0.2 -1 a v mult linear operation range 0 to 3 v v clamp internal clamp level i mult = 1 ma 9 9.5 v output max. slope v mult = 0 to 0.4 v v vff = 0.915 v v comp = upper clamp 0.935 1.34 v/v k m gain (2) v mult = v comp = 0.915 v v comp = 4 v 0.248 0.304 0.360 v error amplifier v inv voltage feedback input threshold tj = 25 c 2.475 2.5 2.525 v 10.3 v < v cc < 22.5 v (1) 2.455 2.545 v cs v mult --------------------- -
electrical characteristics L4984D 10/35 docid024474 rev 1 line regulation v cc = 10.3 v to 22.5 v 2 5 mv i inv input bias current v inv = 0 to 4 v -0.2 -1 a v invclamp internal clamp level i inv = 1 ma 8 9 v gv voltage gain open loop 60 80 db gb gain-bandwidth product 1 mhz i comp source current v comp = 4 v, v inv = 2.4 v 2 4 ma sink current v comp = 4 v, v inv = 2.6 v 2.5 4.5 ma v comp upper clamp voltage i source = 0.5 ma 5.7 6.2 6.7 v burst-mode threshold (1) 2.3 2.4 2.5 lower clamp voltage i sink = 0.5 ma (3) 2.1 2.25 2.4 current sense comparator i cs input bias current v cs = 0 1 a t leb leading edge blanking 145 220 400 ns td (h-l) delay to output 100 200 300 ns v csclamp current sense reference clamp v comp = upper clamp v mult = v vff = 0.915 v (1) 0.84 0.88 0.93 v vcs ofst current sense offset (2) v mult = 0, v vff = 3 v 35 47 mv v mult = 3 v, v vff = 3 v 10 boost inductor saturation detector v cs_th threshold on current sense (1) 1.6 1.7 1.8 v i inv e/a input pull-up current v cs > v cs_th , before restart 5 10 13 a t start restart delay 300 s pfc_ok functions i pfc_ok input bias current v pfc_ok = 0 to 2.6 v -0.1 -1 a v pfc_ok_c clamp voltage i pfc_ok = 1 ma 9 9.5 v v pfc_ok_s ovp threshold (1) voltage rising 2.435 2.5 2.565 v v pfc_ok_r restart threshold after ovp (1) voltage falling 2.34 2.4 2.46 v v pfc_ok_d disable threshold (1) voltage falling 0.12 0.23 0.35 v v pfc_ok_e enable threshold (1) voltage rising 0.15 0.27 0.38 v feedback failure detection v invd feedback failure detection threshold (on v inv ) (1) voltage falling, v pfc_ok = v pfc_ok_s 1.61 1.66 1.71 v voltage feedforward v vff linear operation range 1 3 v table 5. electrical ch aracteristics (continued) symbol parameter test condition min typ max unit
docid024474 rev 1 11/35 L4984D electrical characteristics v dropout v multpk -v vff before turn-on 800 mv after turn-on 20 v vff line drop detection threshold below peak value 25 60 100 mv v vff line drop detection threshold below peak value tj = 0 to 100 c 40 70 100 mv r disch internal discharge resistor 5 10 20 k v dis disable threshold (1) voltage falling 0.745 0.8 0.855 v v en enable threshold (1) voltage rising 0.845 0.88 0.915 v fixed-off-time modulator i timer programming current v mult = 1 v 142 153 163 a t off programmed off-time v mult = 1 v 2.88 3.09 3.30 s r dis discharge resistance 35 60 120 w c timer timing capacitor range 0.1 2.2 nf t off_pk programming range on the peak of v mult 1.45 50 s soft-start t ss activation time 300 s v multx pull-up voltage 10 k from mult to gnd 4.1 v gate driver v ol output low voltage i sink = 100 ma 0.6 1.2 v v oh output high voltage i source = 5 ma 9.8 10.3 v i srcpk peak source current -0.6 a i snkpk peak sink current 0.8 a t f voltage fall time 30 60 ns t r voltage rise time 45 110 ns v oclamp output clamp voltage i source = 5 ma; vcc = 20 v 10 12 15 v uvlo saturation v cc = 0 to v ccon , i sink = 2 ma 1.1 v 1. parameters tracking each other. 2. the multiplier output is given by: table 5. electrical ch aracteristics (continued) symbol parameter test condition min typ max unit ? () 2 5 2 v cs _o fs t vf f v . comp v mult v k cs v m ? ? ? + =
typical electrical performance L4984D 12/35 docid024474 rev 1 4 typical electrical performance figure 3. ic consumption vs. v cc figure 4. ic consumption vs. tj am13219v1 0.001 0.01 0.1 1 10 100 0 5 10 15 20 25 30 icc [ma] vcc [v] vccoff vccon co=1nf f =70khz tj = 25 c am13220v1 0.01 0.1 1 10 -50 -25 0 25 50 75 100 125 150 175 ic current (ma) tj (c) operating quiescent disabled or during ovp latched off before start up vcc=12v co = 1nf f =70khz figure 5. v cc zener voltage vs. tj figure 6. startup & uvlo vs. tj am13221v1 22 23 24 25 26 27 28 -50 -25 0 25 50 75 100 125 150 175 v tj (c) am13222v1 6 7 8 9 10 11 12 13 -50 -25 0 25 50 75 100 125 150 175 v tj (c) vcc-on vcc-off figure 7. feedback reference vs. tj figure 8. e/a output clamp levels vs. tj am13223v1 2.4 2.45 2.5 2.55 2.6 -50 -25 0 25 50 75 100 125 150 175 pin inv (v) tj (c) vcc = 12v am13224v1 0 1 2 3 4 5 6 7 -50 -25 0 25 50 75 100 125 150 175 vcomp (v) tj (c) uper clamp lower clamp vcc = 12v
docid024474 rev 1 13/35 L4984D typical electrical performance figure 9. uvlo saturation vs. tj figure 10. ovp levels vs. tj am13225v1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -50 -25 0 25 50 75 100 125 150 175 v tj (c) vcc = 0v am13226v1 2.36 2.38 2.4 2.42 2.44 2.46 2.48 2.5 -50 -25 0 25 50 75 100 125 150 175 pfc_ok levels (v) tj (c) ovp th restart th figure 11. inductor saturation threshold vs. tj figure 12. v cs clamp vs. tj am13227v1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 -50 -25 0 25 50 75 100 125 150 175 cs pin (v) tj (c) am13228v1 0.85 0.86 0.87 0.88 0.89 0.9 -50 -25 0 25 50 75 100 125 150 175 vcs clamp (v) tj (c) vcomp = upper clamp vcc = v figure 13. timer pin charging current vs. tj fi gure 14. brownout threshold (on vff) vs. tj 100 110 120 130 140 150 160 170 180 190 200 -50 -25 0 25 50 75 100 125 150 175 i tmer (ua) tj (c) am13229v1 am13230v1 0.4 0.5 0.6 0.7 0.8 0.9 1 -50 -25 0 25 50 75 100 125 150 175 v tj (c) enable disable
typical electrical performance L4984D 14/35 docid024474 rev 1 figure 15. r ff discharge vs. tj figure 16. line drop detection threshold vs. tj am13231v1 0 2 4 6 8 10 12 14 16 18 20 -50 -25 0 25 50 75 100 125 150 175 kohm tj (c) am13232v1 0 10 20 30 40 50 60 70 80 90 -50 -25 0 25 50 75 100 125 150 175 mv tj (c) figure 17. v multpk - v vff dropout vs. tj figure 18. pfc_ok enable threshold vs. tj am13233v1 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 -50 -25 0 25 50 75 100 125 150 175 d(mv) tj (c) am13234v1 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 -50-25 0 255075100125150175 th (v) tj (c) on off figure 19. ffd threshold vs. tj am13235v1 1.4 1.5 1.6 1.7 1.8 1.9 2 -50 -25 0 25 50 75 100 125 150 175 v invd (v) tj(c)
docid024474 rev 1 15/35 L4984D typical electrical performance figure 20. multiplier characteristics at v ff =1 v figure 21. multiplier characteristics at v ff =3 v am13236v1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 vcs (v) vmult (v) 2.6 v upper voltage clamp 3.0 v 3.5 v 4.0 v 4.5 v 5.0 v 5.5 v vcomp am13237v1 0 50 100 150 200 250 300 350 400 450 500 0 0.5 1 1.5 2 2.5 3 3.5 vcs (mv) vmult (v) 3.5 v 4.0 v 4.5 v 5.0 v 5.5 v vcomp upper voltage clamp vff = 3 v 3.0 v 2.6 v figure 22. multiplier gain vs. tj figure 23. gate drive clamp vs. tj am13238v1 0.2 0.3 0.4 0.5 -50 -25 0 25 50 75 100 125 150 175 gain (1/v) tj (c) multiplier gain vs. tj vcc = 12v vcomp = 4v vmult = vff = 1v am13239v1 12.65 12.7 12.75 12.8 12.85 12.9 -50 -25 0 25 50 75 100 125 150 175 v tj (c) vcc = 20v figure 24. gate drive output saturation vs. tj figure 25. delay to output vs. tj am13240v1 0 2 4 6 8 10 12 -50 -25 0 25 50 75 100 125 150 175 v tj (c) low level high level am13241v1 50 100 150 200 250 300 -50 -25 0 25 50 75 100 125 150 175 td(h-l) (ns) tj (c) vcc = 12v
application information L4984D 16/35 docid024474 rev 1 5 application information 5.1 theory of operation the L4984D implements conventional ?peak? current mode control, where the on-time ton of the external power switch is determined by the peak inductor current reaching the programmed value. the off-time toff, instead, is determined by a special fixed-off-time (fot) modulator in such a way th at the resulting switching period is constant as long as the boost converter is operated in ccm (i.e. the current in the boost inductor remains greater than zero in a switching cycle). to understand how toff needs to be modula ted to achieve a fixed switching frequency independent of the instantaneous line voltage and the load, it is useful to consider the vs balance equation for the boost inductor under the assumption of ccm operation: equation 1 where vpk is the peak line voltage, vout the regulated output voltage and the instantaneous phase angle of the line voltage. solving for ton, we get: equation 2 then, the switching period t sw is: equation 3 in the end, if t off is changed proportionally to the instantaneous line voltage, i.e. if: equation 4 then t sw is equal to k t v out and, since v out is regulated by the voltage loop, also t sw (and f sw = 1/t sw ) is fixed. this result is based on the sole assumption that the instantaneous line voltage and the output load are such that the boost inductor operates in ccm. () s in vpk vo u t t s in vpk t off on ? = off on t 1 s in vpk vo u t t ? ? ? ? ? ? ? ? ? = off off off off on s w t s in vpk vo u t t t 1 s in vpk vo u t t t t = + ? ? ? ? ? ? ? ? ? = + = = s in vpk k t t off
docid024474 rev 1 17/35 L4984D application information figure 26. line-modulated fixed-off-time modulat or: a) internal block diagram; b) key waveforms with reference to the schematic and the relevant key waveforms in figure 26 , an off-time proportional to the instantaneous line voltage is achieved by charging the capacitor ct with a constant current itimer, accurately fixed in ternally and temperature compensated, while the mosfet is off and commanding mosfet turn-on (and resetting ct at zero) as the voltage across ct equals that on the mult pin. the voltage on this pin is: equation 5 where kp is the divider ratio of the resistors biasing the mult pin. as a result: equation 6 and the switching frequency is: equation 7 the timing capacitor ct, therefore, is selected with the following design formula: equation 8 v out and fsw are design specifications, k p is chosen so that the voltage on the mult pin is within the multiplier linearity range (0 to 3 v) and itimer is specified in section 3: electrical characteristics . am13242v1 mult - + c t i timer off on 0 timer q s r + - pwm comparator driver pwm latch gd cs comp multiplier gd cs s r q t off t on multiplier output mult timer t t t t t t a) b) = s in vpk k v p mult p timer t t p timer t off k i c k s in vpk k i c t = = u t k 1 vo u t c k i t 1 f t t p timer s w s w = = = s w p timer t f vo u t k i c =
application information L4984D 18/35 docid024474 rev 1 along a line half-cycle, toff goes all the way from a minimum near the zero-crossing to a maximum on the sinusoid peak. it is important to check that the off-time occurring on the peak of the voltage sinusoid at minimum input voltage is greater then the minimum programmable value: equation 9 this constraint limits the maximum programmable frequency at: equation 10 as the line rms voltage is increased and/or the output load is decreased, the boost inductor current tends to become discontinuous starting from the region around the zero-crossings. as a result, the switching frequency is no longer constant and tends to increase. however, the frequency rise is significantly lower as compared to that in a transition-mode (tm) operated boost pfc stag e, as illustrated in figure 25 . the switching frequency can exceed fsw.max in the region where the inductor current is discontinuous. figure 27. typical frequency change along a line half-cycle in a boost pfc operated in lm-fot (left) and tm (right) in this example the voltage ripple appearing across the output capacitor cout has been neglected. this ripple at twice the line frequency fl has peak amplitude vout proportional to the output current iout: equation 11 as a consequence, fsw is not ex actly constant but is modulated at 2fl, which spreads the spectrum of the electrical noise injected back into the power lin e and facilitates the compliance with conducted emi emission regulations. the relative frequency change due to the output voltage ripple is: s 1.45 vpk k i c t min p timer t min off > = vo u t vpk 690 f min m a x . s w = [khz] am13243v1 0 0.52 1.05 1.57 2.09 2.62 3.14 0 1 2 3 4 5 6 7 8 9 0 0.52 1.05 1.57 2.09 2.62 3.14 0.4 0.6 0.8 1 1.2 1.4 1.6 vin = 88 vac vin = 264 vac vin = 230 vac normalized switching frequency line voltage phase angle (rad) transition -mode operated pfc vin = 88 vac vin = 264 vac vin = 230 vac normalized switching frequency line voltage phase angle (rad) lm -fot operated pfc vin = 115 vac vin = 115 vac co u t f 4 io u t vo u t l =
docid024474 rev 1 19/35 L4984D application information equation 12 figure 28. line-modulated fixed-off-time-controlled boost pfc: current waveforms as a result of the oper ation of the circuit in figure 26 , the current that the boost pfc pre- regulator draws from the power line is not exactly sinusoidal but is affected by distortion that is lower as the curr ent ripple in the boost inductor is sm aller as compared to its peak value. figure 28 shows some theoretical waveforms, relevant to full load condition, in a line cycle at different input voltages. in the diagram on the left-hand side the line (input) current waveform is shown for different line voltages, while on the right-hand side the envelope of the inductor current at minimum and maximum line voltage is shown. the input current waveform relevant to vin = 88 v ac shows no visible sign of distortion; the operation of the boost inductor is ccm through out the entire line cycle as testified by the inductor current envelope. the brown waveform is relevant to vin = 190 v ac , which is the condition where ccm operation no longer occurs at zero-crossings (this voltage value, for a given power level, depends on the inductance value of the boost inductor); a certain degree of distortion is already visible. vo u t vo u t 1 vo u t vo u t f f s w s w + = am13244v1 line current (a) line voltage phase angle (rad) vin = 88 vac vin = 264 vac vin = 230 vac vin = 190 vac line current inductor current (a) line voltage phase angle (rad) vin = 88 vac vin = 264 vac boost inductor current envelope
application information L4984D 20/35 docid024474 rev 1 figure 29. line-modulated fixed-off-time-controlled boost pfc: input current harmonic contents the waveform relevant to vin = 264 v ac shows the highest degree of distortion and the largest portion of the line cycle where boos t inductor operates in discontinuous mode (dcm). however, its harmonic content, shown in figure 29 , is still so low that it is not an issue for emc compliance. almost all the distor tion is concentrated in the third harmonic, whose amplitude is 17% of the fundamental one, while the thd is 17.7%. am13245v1 vin = 264vac thd = 17.7% harmonic order (n) % harmonic amplitude (normalized to fundamental)
docid024474 rev 1 21/35 L4984D overvoltage protection (ovp) 6 overvoltage protection (ovp) normally, the voltage control loop keeps the output voltage vout of the pfc pre-regulator close to its nominal value, set by the ratio of th e resistors r1 and r2 of the output divider. a pin of the device (pfc_ok) has been dedicat ed to monitor the output voltage with a separate resistor divider (r3 high, r4 low, see figure 30 ). this divider is selected so that the voltage at the pin reaches 2.5 v if the ou tput voltage exceeds a preset value, usually larger than the maximum vout that can be expected. figure 30. output voltage setting, ovp a nd ffd functions: internal block diagram note: example: v out = 400 v, v outx = 434 v. select: r3 = 8.8 m; then: r4 = 8.8 m 2.5/(434-2.5) = 51 k. when this function is trigger ed, the gate drive activity is immediately stopped until the voltage on the pin pfc_ok drops below 2.4 v. notice that r1, r2, r3 and r4 can be selected without any constraints. the unique cr iterion is that both dividers must sink a current from the output bus which needs to be significantly higher than the bias current of both pins inv and pfc_ok (< 1 a). am13246v1 frequency compensation 2.5 v + - 0.23 v 0.27 v - + inv disable ovp error amplifier comp 2.5 v 2.4 v + - 1.66 v l_ovp 6 1 2 - + pfc_ok vout r1a r1b r2 r3a r3b r4 r3 r1 L4984D
feedback failure detection (ffd) L4984D 22/35 docid024474 rev 1 7 feedback failure detection (ffd) the ovp function handles ?normal? overvoltage conditions, i.e. those resulting from an abrupt load/line change or occurring at star tup. if the overvoltage is generated by a feedback failure, for instance when the upper resistor of the output divider (r1) fails open, eventually the error amplifier output (comp) saturates high and the voltage on its inverting input (inv) drops from its steady-sate value (2 .5 v). an additional co mparator monitors the voltage on the inv pin, comparing it against a reference located at 1.66 v. when the voltage on pin pfc_ok exceeds 2.5 v and, simultaneously, that on the inv pin falls below 1.66 v, the ffd function is triggered: t he gate drive activity is imme diately stopped, the device is shut down and its quiescent consumption reduced. this condition is latched and to restart the ic it is necessary to recycl e the input power, so that the v cc voltage goes below 6 v. the pin pfc_ok doubles its function as a not -latched ic disable: a voltage below 0.23 v shuts down the ic, reducing its consumption below 2 ma. to restart, simply let the voltage on the pin go above 0.27 v. note that these functions offer complete protection against not only feedback loop failures or erroneous settings , but also against a failure of the protection itself. either resistor of the pfc_ok divider failing short or open or a pin pfc_ok floating results in shutting down the ic and stopping the pre-regulator.
docid024474 rev 1 23/35 L4984D voltage feedforward 8 voltage feedforward the power stage gain of pfc pre-regulators varies with the square of the rms input voltage. so does the crossover frequency fc of the overall open-loop gain because the gain has a single pole characteristic. this le ads to large trade-offs in the design. for example, setting the gain of the error amplifier to get fc = 20 hz at 264 v ac means having fc = 4 hz at 88 v ac , resulting in a sluggish control dynamics. additionally, the slow control loop causes large transient current flow during rapid line or load changes that are limited by the dynamics of the multiplier outpu t. this limit is consi dered when selecting the sense resistor to let the full load power pass under minimum line voltage conditions, with some margin. but a fixed current limit allows excessive power input at high line, whereas a fixed power limit requires the current limit to vary inversely with the line voltage. input voltage feedforward compensates for the gain variation with the line voltage and allows all of the above-mentioned issues to be minimized. it consists of deriving a voltage proportional to the input rms voltage, feeding this voltage into a squarer/divider circuit (1/v2 corrector) and providing the resulting signa l to the multiplier that generates the current reference for the inner current control loop (see figure 31 ). figure 31. voltage feedforward: squarer-divider (1/v2) block diagram and transfer characteristic in this way, if the line voltage doubles the amplitude of the multiplier, output is halved and vice versa, so that the current reference is adapted to the new operating conditions with (ideally) no need to invoke the slow response of the error amplifier. additionally, the loop gain is constant throughout the input voltag e range, which improves significantly dynamic behavior at low line and simplifies loop design. actually, deriving a voltage proportional to th e rms line voltage implies a form of integration, which has its own time constant. if it is too small, the voltage generated is affected by a considerable amount of ripple at twice the ma ins frequency that causes distortion of the current reference (resulting in high thd and poor pf); if it is too large there is a considerable delay in setting the right amount of feedforward, resulting in excessive overshoot and undershoot of the pre-regulator output voltage in response to large line voltage changes. clearly, a trade-off is required. the L4984D realizes a new voltage feedforward that, using just two external parts, strongly minimizes this time constant trade-off issue whichever voltage change occurs on the mains, am13248v1 01234 0 0.5 1 1.5 2 v ff =v mult vcsx 0.8 v comp =4v actual ideal 5 mult 3 rectified mains "ideal" diode current reference (vcsx) 9.5v vff c ff r ff e/a output (v comp ) - + 1/v 2 multiplier L4984D detector mains drop
voltage feedforward L4984D 24/35 docid024474 rev 1 both surges and drops. a capacitor c ff and a resistor r ff , connected from the vff pin to ground, complete an internal peak-holding circ uit that provides a dc voltage equal to the peak of the voltage applied on the mult pin. in th is way, in case of sudden line voltage rise, c ff is rapidly charged through the low impedance of the internal diode; in case of line voltage drop, an internal ?mains drop? detector enables a low impedance switch that suddenly discharges c ff , therefore reducing the settling time needed to reach the new voltage level. the discharge of c ff is stopped when either its voltage equals the voltage on the mult pin or the voltage on the vff pin falls below 0.88 v, to prevent the ?brownout protection? function from being improperly activated (see section 12: power management and housekeeping functions ). with this functionality, an ac ceptably low steady-state ripple of the vff voltage (and, then, low current distortion) can be achieved with a limited undershoot or overshoot on the pre-regulator output during line transients. the twice-mains-frequency (2 ? fl) ripple appearing across c ff is triangular with peak-to- peak amplitude that, with good approximation, is given by: equation 13 where fl is the line frequency. the amount of 3rd harmonic distortion introduced by this ripple, related to the amplitude of its 2 ? fl component, is: equation 14 figure 32 shows a diagram that helps choose the time constant r ff c ff based on the amount of maximum desired 3rd harmonic distortion. note, however, that there is a minimum value for the time constant r ff c ff below which improper activation of the vff fast discharge may occur. in fact, t he twice-mains-frequency ripple across c ff under steady-state conditions must be lower than the minimum line drop detection threshold ( v vff_min = 40 mv). therefore: equation 15 always connect r ff and c ff to the pin; the ic does not work properly if the pin is left floating or may be damaged if connected directly to ground. ff ff l multpk ff c r f 4 1 v 2 v + = ff ff l 3 c r f 2 100 % d = min _ l min _ vff m a x _ multpk ff ff f 4 1 v v 2 c r ? > ?
docid024474 rev 1 25/35 L4984D voltage feedforward figure 32. r ff c ff as a function of 3rd harmonic distortion introduced in the input current am13247v1 d % 3 0.1 1 10 0.01 0.1 1 10 f = 50 hz l f = 60 hz l r c [s] ff ff
soft-start L4984D 26/35 docid024474 rev 1 9 soft-start to reduce inrush energy at startup or after an auto-restart protection tripping, the L4984D uses soft-start. please refer to table in section 12: power management and housekeeping functions for more details of the events triggering soft-start. the function is performed by internally pulling the voltage on the mult pin towards an asymptotic level located at about 4.1 v as the device wakes up. this has a twofold effect: on the one hand, the output of the multiplier is lowered through the voltage feedforward function, therefore programming a lower peak curr ent; on the other hand, the off-time of the power switch is considerably prolonged with respect to the normal values programmed by the capacitor connected to the timer pin. in this way, both the current inrush and the risk of saturating the boost inductor at startup are minimized. after 300 s from its activation, the pull-up is released. the voltage on the mult pin decays with the time constant determined by the resistor divider that biases the pin and the bypass capacitor typically connected between the pin an d ground to reduce noise pick-up. at the same time, c ff is discharged by turning on the internal low impedance discharge switch (see section 8: voltage feedforward ). the soft-start function is performed at turn-on by vcc turn-on threshold (v ccon ), by the brownout function and at startup by pfc_ok. on the following activations by pfc_ok (like during burst-mode operation driven by a d2d conv erter controller) the soft-start function is not performed. figure 33 shows the different startup mechan isms and the activations of the soft-start function. figure 33. startup mechanisms and activations of the soft-start function 3)&b2.b(' *' 3)&b2. 08/7 9&& 67$57 83 %<9&& 67$57 83 %<3)&b2. %52:1,1287 %856702'( %<''&219 62)767$57 1262)767$57 9 (1 0$,16',3 9&& 5(&<&/( w $09
docid024474 rev 1 27/35 L4984D inductor saturation detection 10 inductor saturation detection boost inductor hard saturation may be a fatal event for a pfc pre-regulator: the current upslope becomes so large (50-100 times steeper, see figure 34 ) that, during the current sense propagation delay, the current may reach abnormally high values. the voltage drop caused by this abnormal current on the sense resistor reduces the gate-to-source voltage, so that the mosfet may work in the active region and dissipate a huge amount of power, which leads to a catastrophic fa ilure after few switching cycles. however, even a well-designed boost inductor may occasionally saturate when the boost stage recovers after a missing line cycle. this happens when the restart occurs at an unfavorable line voltage phase, i.e. when the ou tput voltage is lower than the rectified input voltage as this reappears. as a result, in the boost inductor the inrush current coming from the bridge rectifier and going to the output capacitor adds up to the switched current. furthermore, there is little or no voltage available for demagnetization. to cope with a saturated inductor, the L4984D is provided with a second comparator on the current sense pin (cs, pin 4) that stops the ic if the voltage, normally limited within 0.88 v, exceeds 1.7 v. after that, the ic is restarted by the internal starter circuitry; the starter repetition time is low enough (300 s typ.) to guarantee low stress for the inductor, the power mosfet and the boost diode. figure 34. effect of boost inductor saturation on mosfet current and detection method am13249v1 t delay di l multiplier output vcs t 1.7v t delay t t delay t inductor not saturating inductor slightly saturating inductor saturating hard multiplier output multiplier output 1.7v 1.7v di l di l vcs vcs
thd optimizer circuit L4984D 28/35 docid024474 rev 1 11 thd optimizer circuit the L4984D is provided with a special circuit that reduces the conduction dead-angle occurring at the ac input current near the ze ro-crossings of the line voltage (crossover distortion). in this way the thd (total harmonic distortion) of the current is considerably reduced. a major cause of this distortion is the inability of the system to transfer energy effectively when the instantaneous line voltage is very low. this effect is magnified by the high- frequency filter capacitor placed after the bridge rectifier, which retains some residual voltage that causes the diodes of the bridge rectifier to be reverse-biased and the input current flow to temporarily stop. to overcome this issue the device forces the pfc pre-regulator to process more energy near the line voltage zero-crossings as comp ared to that commanded by the control loop. this results in both minimizing the time interval where energy transfer is lacking and fully discharging the high-frequency filter capacitor after the bridge. figure 35. thd op timizer circuit am13250v1 + + mult comp t @ vac1 @ vac2 > vac1 t t to pwm comparator multiplier offset generator t vff 1 / v 2 t t
docid024474 rev 1 29/35 L4984D thd optimizer circuit figure 36. hd optimization: standard pfc controller figure 35 shows the internal block diagram of the thd optimizer circuit. to take maximum benefit from the thd optimizer circuit, the high-frequency filter capacitor after the bridge rectifier should be minimized, compatibly with emi f iltering needs. a large capacitance, in fact, introduces a conduction dead-angle of the ac input current - even with an ideal energy transfer by the pfc pre-regulator - therefore reducing the effectiveness of the optimizer circuit. essentially, the circuit artificially increases th e on-time of the power switch with a positive offset added to the output of the multiplier in the proximity of the line voltage zero-crossings. this offset is reduced as the instantaneous line voltage increases, so that it becomes negligible as the line voltage moves toward the top of the sinusoid. furthermore, the offset is modulated by the voltage on the vff pin (see section 8: voltage feedforward ) so as to have little offset at low line, where energy transfer at zero-crossings is typically quite good, and a larger offset at high line where the energy transfer gets worse. the effect of the circuit is shown in figure 36 , where the key waveforms of a standard pfc controller are compared to those of this chip. note the significant reduction in the region around the zero-crossing where the drain voltage cannot reach the output voltage and how switching frequency drops dramatically near the zero-crossing.
power management and housekeeping functions L4984D 30/35 docid024474 rev 1 12 power management and housekeeping functions a communication line with the control ic of the cascaded dc-dc converter can be established via the disable function included in the pfc_ok pin (see section 7: feedback failure detection (ffd) for more details). typically this line is used to allow the pwm controller of the cascaded dc-dc converter to shut down the L4984D in case of light load and to minimize the no-load input consumption. should the residual c onsumption of the chip be an issue, it is also possible to cut down th e supply voltage. interface circuits like those are shown in figure 37 . needless to say, this operation assumes that the cascaded dc-dc converter stage works as the master and the pfc stage as the slave or, in other words, that the dc-dc stage starts first; it powers both cont rollers and enables/disables the operation of the pfc stage. figure 37. interface circuits that let dc-dc converter controller ic disable the L4984D another available function is brownout protection, which is basically a not-latched shutdown function that is activated when a condition of mains undervoltage is detected. this condition may cause overheating of the primary power section due to an excess of rms current. brownout can also cause the pfc pre-regulator to work in open loop, which may be dangerous to the pfc stage itself and the down stream converter, should the input voltage return abruptly to its rated value. another problem is the spurious restarts that may occur during converter power-down and that cause th e output voltage of the converter to not decay to zero monotonically. for these reasons it is usually preferable to shut down the unit in the case of brownout. the brownout threshol d is internally fixed at 0.8 v and is sensed on the vff pin while the voltage is falling. an 80 mv hysteresis prevents rebounding at input voltage turn-off. the soft-start function is performed by pfc_ok enable threshold (v pfc_ok_e ) only at startup, but not on the following activations, to ensure a proper burst-mode operation (as described in figure 33 ). for this reason pin mult is suggested to be used as remote on/off control. in table 6 it is possible to find a summary of a ll of the above mentioned working conditions that cause the device to stop operating. am13252v1 l6566a v cc _pfc 6 L4984D v cc 10 v cc 5 l6599a pfc_stop 9 L4984D pfc_ok 6 l6591 pfc_stop 8 L4984D pfc_ok 6
docid024474 rev 1 31/35 L4984D power management and housekeeping functions table 6. summary of L4984D idle states condition caused or revealed by ic behavior restart condition typical ic consumption ss activation uvlo v cc < v ccoff disabled v cc > v ccon 65 a yes standby v pfc_ok < v pfc_ok_d stop switching v pfc_ok > v pfc_ok_e 1.5 ma no ac brownout v vff < v dis stop switching v vff > v en 1.5 ma yes ovp v pfc_ok > v pfc_ok_s stop switching v pfc_ok < v pfc_ok_r 2.2 ma no feedback failure v pfc_ok > v pfc_ok_s and v inv < 1.66 v latched-off v cc < v ccrestart then v cc > v ccon 180 a yes low consumption v comp < 2.4 v burst mode v comp > 2.4 v 1.8 ma no saturated boost inductor vcs > v cs_th stop switching auto restart after 300 s 4 ma no
package mechanical data L4984D 32/35 docid024474 rev 1 13 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions a nd product status are available at: www.st.com . ecopack is an st trademark. table 7. sso10 mechanical data dim databook (mm) typ min max a 1.75 a1 0.10 0.25 a2 1.25 b 0.31 0.51 c 0.17 0.25 d 4.90 4.80 5 e 6 5.80 6.20 e1 3.90 3.80 4 e 1 h 0.25 0.50 l 0.40 0.90 k 0 8
docid024474 rev 1 33/35 L4984D package mechanical data figure 38. sso10 package dimensions 8140761 rev. a
revision history L4984D 34/35 docid024474 rev 1 14 revision history table 8. document revision history date revision changes 15-apr-2013 1 initial release.
docid024474 rev 1 35/35 L4984D please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not authorized for use in weapons. nor are st products designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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